The Chisel Working Group is dedicated to improving the productivity of digital design and verification to enable next-generation SoC designs based on open-source tools. Its namesake project, Chisel HDL, is a domain-specific language embedded in Scala that provides designers with modern programming techniques like object orientation, functional programming, parameterized types, and type inference. CWG also includes FIRRTL, the hardware compiler framework that enables decoupling design from implementation via target specialization and custom transformations. In this talk, you’ll learn about the exciting improvements to the various projects, as well as the adoption of formal governance.